It has been decades since Intel tried to tempt the sector with a brand new Itanium chip. The VLIW 64-bit processor last received a significant update in 2008, with the two-billion transistor Tukwila . Now Chipzilla is upping the ante — moving to 32nm process, adding as much as four more cores, and tacking on a couple of billion additional transistors. Poulson also adds a brand new feature called Intel Instruction Replay Technology, which adds a buffer for more quickly recovering from errors, allowing the chip to select up from the last known good instruction as opposed to having to utterly flush the pipeline. Those seeking to upgrade can be happy to listen to that the approaching IA-64 CPU is pin compatible with Tukwila, so customers can simply drop the hot processor in to existing systems. Inspect the total PR after the break.
Aug. 19, 2011 – Intel Corporation today revealed architecture features of the subsequent Itanium processor codenamed âPoulson. Scheduled for launch in 2012, âPoulson, one of the most sophisticated Intel processor up to now, will offer the strongest RAS features in addition to the largest leap in performance in comparison with previous Itanium generations.
New disclosed features:
Intel Instruction Replay Technology – New capability to enable errant instructions to be re-issued and thereby automatically get over severe errors to assist prevent system crashes and knowledge corruptions.
Similarly, Poulson adds extensive RAS protection to almost the entire major structures within the Itanium core design. This includes the Last Level Cache (LLC), Mid-level Instruction cache (MLI), Mid-level Data cache (MLD), Integer Execution Unit (IEU) and Floating Point Unit (FPU), to call a couple of.
Intel Hyper-Threading Technology, enhanced with dual-domain multi-threading support – new architecture enables independent front and backend pipeline execution to enhance multi-thread efficiency and function.
Major hardware investments on multi-threading include: dual threaded register files, dual threaded data side Translation buffers (TLBs), and a brand new fairness mechanism. Together, these additions enable the twin domain multi-threading support to noticeably improve Poulson’s multi-threading performance over that of the former generation.
Intel Itanium New Instructions — new instructions simplify common tasks and branch operations to assist take future Itanium performance to the subsequent level and to put the inspiration for the way forward for Itanium computing.
The above features are âdesigned to take full benefit of the 8-core, 12-wide issue architecture by enabling the utmost amount of parallel execution,â said Pauline Nist, General Manager of Mission Critical Segment at Intel. Poulson is on target for 2012 delivery and the follow-on future Kittson processor is under development.
Additional “Poulson” Highlights:
Eight high-capacity cores
54MB on-die memory (50MB SRAM)
3.1 billion transistors on 32nm process technology
33 percent higher system bandwidth improvement with higher bus speeds (QPI and SMI)
Next-generation architecture with new data and instruction pipelines, floating-point
pipeline and instruction buffers
2x max execution width vs. current architecture from 6- to twelve-issue
Advances in reliability, availability and serviceability (RAS) features
Improved power management features and reduced overall socket power consumption
Pin compatibility with the present Intel Itanium 9300 Processor Series
About Intel
Intel (NASDAQ: INTC) is a worldwide leader in computing innovation. The corporate designs and builds the fundamental technologies that function the root for the world’s computing devices. Additional info about Intel is obtainable at newsroom.intel.com and blogs.intel.com.
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